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| Derechos | Preview | Fecha Public. | Título | Autor(es) | Tipo |
| openAccess |  | 2008 | c-element ndr | Avedillo, María J. CSIC ORCID; Núñez, Juan CSIC ORCID ; Quintana, J. M. CSIC ORCID | topografía de productos semiconductores |
| openAccess |  | 2012 | Compact and power efficient MOS-NDR muller C-elements | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess | | 2016 | Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID | artículo |
| openAccess |  | 2017 | Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID | artículo |
| openAccess |  | 2017 | Complementary tunnel gate topology to reduce crosstalk effects | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2009 | conexiones mos ndr | Avedillo, María J. CSIC ORCID; Núñez, Juan CSIC ORCID ; Quintana, J. M. CSIC ORCID | topografía de productos semiconductores |
| closedAccess |  | feb-1995 | Constrained state assignment of easily testable FSMs | Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID; Huertas-Díaz, J. L. CSIC | artículo |
| openAccess |  | 2002 | COPAS: A new algorithm for the partial input encoding problem | Martínez, Manuel; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID; Huertas-Díaz, J. L. CSIC | artículo |
| openAccess |  | 2008 | Design of RTD-based NMIN/NMAX gates | Núñez, Juan CSIC ORCID ; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2014 | DOE based high-performance gate-level pipelines | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintero, Héctor CSIC | comunicación de congreso |
| openAccess |  | 2012 | Domino inspired MOBILE networks | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | artículo |
| openAccess |  | 2023 | Effect of device mismatches in differential oscillatory neural networks | Shamsi, Jafar CSIC ORCID; Avedillo, María J. CSIC ORCID; Linares-Barranco, Bernabé CSIC ORCID; Serrano-Gotarredona, Teresa CSIC ORCID | artículo |
| openAccess |  | 2009 | Efficient realisation of MOS-NDR threshold logic gates | Núñez, Juan CSIC ORCID ; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID | artículo |
| openAccess |  | 2001 | Efficient realization of a threshold voter for self-purging redundancy | Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID; Huertas-Díaz, J. L. CSIC | artículo |
| openAccess |  | 2011 | Efficient realization of RTD-CMOS logic gates | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 1992 | Efficient state reduction methods for PLA-based sequential circuits | Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID; Huertas-Díaz, J. L. CSIC | artículo |
| openAccess |  | 2011 | Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2010 | Evaluation of RTD-CMOS logic gates | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 4-dic-2023 | Experimental demonstration of coupled differential oscillator networks for versatile applications | Jiménez Través, Manuel CSIC ORCID ; Núñez, Juan CSIC ORCID ; Shamsi, Jafar CSIC ORCID; Linares-Barranco, Bernabé CSIC ORCID; Avedillo, María J. CSIC ORCID | artículo |
| openAccess |  | 2014 | Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | artículo |
