English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/84116
logo share SHARE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:


Efficient realization of RTD-CMOS logic gates

AuthorsNúñez, Juan ; Avedillo, M. J. ; Quintana, J. M.
Issue Date2011
PublisherAssociation for Computing Machinery
CitationProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI: 387-390 (2011)
AbstractThe incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined. Lower average power and energy per cycle are obtained for RTD/CMOS implementations.
DescriptionTrabajo presentado al 21st GLSVLSI celebrado en New York en 2011.
Publisher version (URL)http://dx.doi.org/10.1145/1973009.1973090
Identifiersdoi: 10.1145/1973009.1973090
isbn: 978-1-4503-0667-6
Appears in Collections:(IMSE-CNM) Libros y partes de libros
Files in This Item:
File Description SizeFormat 
Efficient Realization.pdf189,72 kBAdobe PDFThumbnail
Show full item record
Review this work

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.