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| Derechos | Preview | Fecha Public. | Título | Autor(es) | Tipo |
| openAccess |  | 2010 | Redes MOBILE MOS-NDR operando con reloj de una fase | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2017 | Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID | artículo |
| closedAccess |  | 2003 | Review of capacitive threshold gate implementations | Beiu, V.; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2008 | RTD based logic circuits using generalized threshold gates | Pettenghi, Héctor CSIC ORCID; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2011 | RTD-CMOS pipelined networks for reduced power consumption | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | artículo |
| closedAccess |  | 2006 | Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors | Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID; Pettenghi, Héctor CSIC ORCID | artículo |
| closedAccess |  | 2004 | Simplified reed-muller expressions for residue threshold functions | Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID; Huertas-Díaz, J. L. CSIC | artículo |
| openAccess |  | 2011 | Simplified single-phase clock scheme for MOBILE networks | Núñez, Juan CSIC ORCID ; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID | artículo |
| closedAccess |  | 2006 | Single phase clock scheme for mobile logic gates | Pettenghi, Héctor CSIC ORCID; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | artículo |
| openAccess |  | 2010 | Single phase MOS-NDR mobile networks | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 1998 | Sorting networks implemented as νMOS circuits | Rodríguez-Villegas, E. CSIC; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID; Rueda, Adoración CSIC ORCID | artículo |
| openAccess |  | jul-1994 | State merging and state splitting via state assignment: a new FSM synthesis algorithm | Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID; Huertas-Díaz, J. L. CSIC | artículo |
| openAccess |  | 2020 | Steep-slope Devices for Power Efficient Adiabatic Logic Circuits | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID | comunicación de congreso |
| closedAccess |  | 2008 | Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode | Romeira, Bruno; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID | artículo |
| openAccess |  | 2000 | Threshold logic based adders using floating-gate circuits | Rodríguez-Villegas, E. CSIC; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID; Rueda, Adoración CSIC ORCID | comunicación de congreso |
| openAccess | | 2013 | Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| openAccess |  | 2012 | Two-phase RTD-CMOS pipelined circuits | Núñez, Juan CSIC ORCID ; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | artículo |
| openAccess |  | 14-ago-2007 | Using Multi-Threshold Threshold Gates in RTD-based Logic Design. A Case Study | Pettenghi, Héctor CSIC ORCID; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | comunicación de congreso |
| closedAccess |  | 2008 | Using multi-threshold threshold gates in RTD-based logic design: A case study | Pettenghi, Héctor CSIC ORCID; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID | artículo |
| closedAccess |  | 2003 | VLSI implementations of threshold logic-a comprehensive survey | Beiu, V.; Quintana, J. M. CSIC ORCID; Avedillo, María J. CSIC ORCID | artículo |
