English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/227194
logo share SHARE   Add this article to your Mendeley library MendeleyBASE
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE
Exportar a otros formatos:


Steep-slope Devices for Power Efficient Adiabatic Logic Circuits

AuthorsNuñez, Juan; Avedillo, María J.
Issue Date2020
PublisherConference on Design of Circuits and Integrated Systems
CitationXXXV Conference on Design of Circuits and Integrated Systems (2020)
AbstractReducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope (SS), and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account the problems associated with their inverse current due to their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially at medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits, both at gate and architecture levels, with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs. Index Terms—Adiabatic logic, Tunnel
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
Files in This Item:
File Description SizeFormat 
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits.pdf894,04 kBAdobe PDFThumbnail
Show full item record
Review this work

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.