| Derechos | Preview | Fecha Public. | Título | Autor(es) | Tipo |
| closedAccess |  | 2017 | A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs | Martín-Lloret, P. CSIC; Toro-Frias, A. CSIC; Martín-Martínez, Javier; Castro-López, R. CSIC ORCID ; Roca, Elisenda CSIC ORCID ; Rodríguez, R.; Nafría, Montserrat; Fernández, Francisco V. CSIC ORCID | comunicación de congreso |
| closedAccess |  | 2012 | An automated layout-aware design flow | Toro-Frias, A. CSIC; Castro-López, R. CSIC ORCID ; Roca, Elisenda CSIC ORCID ; Fernández, Francisco V. CSIC ORCID | comunicación de congreso |
| openAccess |  | 19-abr-2021 | Circuit reliability prediction: Challenges and solutions for the device time-dependent variability characterization roadblock | Nafria, M.; Diaz-Fortuny, J.; Saraza-Canflanca, P. CSIC ORCID; Martín-Martínez, Javier; Roca, Elisenda CSIC ORCID ; Castro-López, R. CSIC ORCID ; Rodríguez, R.; Martín-Lloret, P. CSIC; Toro-Frias, A. CSIC; Mateo, D.; Barajas, E.; Aragones, X.; Fernández, Francisco V. CSIC ORCID | comunicación de congreso |
| openAccess | | 14-may-2019 | Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator | Toro-Frias, A. CSIC; Saraza-Canflanca, P. CSIC ORCID; Passos, F.; Martin-Lloret, P.; Castro-López, R. CSIC ORCID ; Roca, E.; Martin-Martinez, J.; Rodriguez, R.; Nafria, M.; Fernandez, F. V. | comunicación de congreso |
| closedAccess |  | 2011 | Layout-aware pareto fronts of electronic circuits | Toro-Frias, A. CSIC; Castro-López, R. CSIC ORCID ; Roca, Elisenda CSIC ORCID ; Fernández, Francisco V. CSIC ORCID | comunicación de congreso |
| closedAccess |  | sep-2016 | Reliability simulation for analog ICs: Goals, solutions, and challenges | Toro-Frias, A. CSIC; Martín-Lloret, P. CSIC; Martín-Martínez, Javier; Castro-López, R. CSIC ORCID ; Roca, Elisenda CSIC ORCID ; Rodríguez, R.; Nafría, Montserrat; Fernández, Francisco V. CSIC ORCID | artículo |
