Analysis of the influence of the biasing circuit on the performance of a low noise amplifier with feedback

Abstract

In this paper we present a comparative study among different biasing circuits of a inductorless low-area Low Noise Amplifier (LNA) with feedback. With this study, we intend to determine the most suitable biasing circuit to achieve the best LNA performance. The LNAs under study are simulated in two different CMOS processes, 130 nm and 90 nm, to validate our conclusions in different technologies. The voltage supply in both cases is 1.2 V. The best LNA implemented in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltge gain (Av) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology implemented in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are imput impedance marched and have a noise figure below 2.4 dB measured at 2.4 GHz. The layout of noise figure below 2.4 dB measured at 2.4 GHz. The layout of the LNA siumlated in the 130 nm technology was designed achieving an area of 0.012 mm2, wiich is near the size of a pad or an inductor.