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Título: | Layout-aware pareto fronts of electronic circuits |
Autor: | Toro-Frias, A. CSIC; Castro-López, R. CSIC ORCID ; Roca, Elisenda CSIC ORCID ; Fernández, Francisco V. CSIC ORCID | Fecha de publicación: | 2011 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | 20th European Conference on Circuit Theory and Design (ECCTD): 345-348 (2011) | Resumen: | Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such as the yield or the reconfiguration capabilities. However, the effect of layout parasitics is the factor that has been missing in the literature: the accuracy may be seriously degraded by layout parasitics not considered during the front generation. In this paper, we present a technique to generate layout-aware Pareto fronts that accurately accounts for the impact of both geometry and parasitics. | URI: | http://hdl.handle.net/10261/83813 | DOI: | 10.1109/ECCTD.2011.6043357 | Identificadores: | doi: 10.1109/ECCTD.2011.6043357 isbn: 978-1-4577-0617-2 |
Aparece en las colecciones: | (IMSE-CNM) Libros y partes de libros |
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accesoRestringido.pdf | 15,38 kB | Adobe PDF | Visualizar/Abrir |
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