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Título: | Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure |
Autor: | Acosta, Antonio J. CSIC ORCID; Barriga, Angel CSIC ORCID; Bellido, M. J.; Valencia-Barrero, M. CSIC ORCID; Huertas-Díaz, J. L. CSIC | Fecha de publicación: | 1998 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | IEE Proceedings Circuits, Devices and Systems 145(4): 247-253 (1998) | Resumen: | The authors describe the design, integration and characterisation of a bit-level pipelined self-timed multiplier architecture. The differential structure SODS (switched-output differential structure) has been used for computation blocks and the PLCAR structure (protocol and latching controlled by acknowledge and request) for the interface blocks, introduced in an array-based architecture. A 4 x 4-bit multiplier has been integrated in a l.Oum CMOS technology and the proposed architecture has been compared with other asynchronous approaches, showing a considerable improvement, up to 50% in terms of area, speed and power consumption. Compared with a synchronous approach, the main advantage of the proposed architecture is a lower power consumption below a certain incoming input data rate, but at the expense of area and speed. © IEE, 1998. | URI: | http://hdl.handle.net/10261/84913 | DOI: | 10.1049/ip-cds:19982125 | Identificadores: | doi: 10.1049/ip-cds:19982125 issn: 1350-2409 |
Aparece en las colecciones: | (IMSE-CNM) Artículos |
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