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Título: | AES T-Box tampering attack |
Autor: | Cabrera Aldaya, Alejandro; Cabrera Sarmiento, Alejandro J.; Sánchez-Solano, Santiago CSIC ORCID | Palabras clave: | AES Tampering T-Box Ciphertext-only attack FPGA Bitstream |
Fecha de publicación: | abr-2016 | Editor: | Springer Nature | Citación: | Journal of Cryptographic Engineering 6(1): 31-48 (2016) | Resumen: | The use of embedded block memories (BRAMs) in Xilinx FPGA devices makes it possible to store the T-Boxes that are employed to implement the AES block cipher’s SubBytes and MixColumns operations. Several studies into BRAM resistance to side-channel attacks have been reported in the literature, whereas this paper presents a novel attack based on tampering the BRAMs storing the T-Boxes. This approach allows recovering the key using a ciphertext-only attack for all AES key sizes. The complexity of the attack makes it completely feasible. The attack was mounted against previously reported FPGA-based AES implementations, taking into account the different design criteria used in each case and focusing mainly on the implementation of the final round of the AES algorithm, which plays a crucial role in the analysis. Three different final round implementations extracted from well-known existing architectures are analyzed in this work. The paper also discusses some countermeasures with regard to security, performance and FPGA resource utilization. The attack is presented against FPGA-based implementations but it can be extended to software architectures as well. | Versión del editor: | https://doi.org/10.1007/s13389-015-0103-4 | URI: | http://hdl.handle.net/10261/195094 | DOI: | 10.1007/s13389-015-0103-4 |
Aparece en las colecciones: | (IMSE-CNM) Artículos |
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