Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA

Abstract

This paper presents the design implementation and experimental characterization of an adaptive Low Noise Amplifier (LNA) intended for multi-standard Radio Frequency (RF) wireless transceivers. The circuit —fabricated in a 90-nm CMOS technology— is a two-stage inductively degenerated common-source topology that combines PMOS varactors with programmable load to make the operation of the circuit continuously tunable. Practical design issues are analyzed, considering the effect of circuit parasitics associated to the chip package and integrated inductors, capacitors and varactors. Experimental measurements show a continuous tuning of NF and Sparameters within the 1.75-2.23GHz band, featuring NF<3.7dB, S21 >19.6dB and IIP3> −9.8dBm, with a power dissipation < 23mW from a 1-V supply voltage.