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Campo DC | Valor | Lengua/Idioma |
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dc.contributor.author | Zamarreño-Ramos, Carlos | - |
dc.contributor.author | Serrano-Gotarredona, Rafael | - |
dc.contributor.author | Serrano-Gotarredona, Teresa | - |
dc.contributor.author | Linares-Barranco, Bernabé | - |
dc.date.accessioned | 2013-11-20T10:23:54Z | - |
dc.date.available | 2013-11-20T10:23:54Z | - |
dc.date.issued | 2008 | - |
dc.identifier.citation | IEEE International Symposium on Circuits and Systems: 644-647 (2008) | es_ES |
dc.identifier.isbn | 978-1-4244-1683-7 | - |
dc.identifier.uri | http://hdl.handle.net/10261/87092 | - |
dc.description | Comunicación presentada al "ISCAS'08" celebrado en Seattle (USA) del 18 al 21 de Mayo de 2008. | es_ES |
dc.description.abstract | This paper presents the design and simulation of a serial AER LVDS communication link. It converts data from classical AER parallel bus with a 4-phase handshaking protocol into a bit stream which is transmitted serially into a single LVDS wire. At the receiver side data from the LVDS cable are transformed back to a parallel AER bus and handshaking signals are also properly managed. The link has been designed in a 90 nms technology. Extensive simulations have been performed demonstrating that the link can operate at a speed of 1 Gbps for all the technology corners, exhibiting a power consumption of 27.8 mW for the transmitter and 12.3 mW for the receiver. In the simulation the transmission channel was modelled as a 50 cm cat5E UTP cable, connected to the AER chip through 5 cm PCB traces modelled as a coupled microstrip transmission line. The design has been completed up to the layout level and has been submitted for fabrication. The transmitter and the receiver take up an area of 311times148 mum2 and 300x148 mum2 respectively. | es_ES |
dc.description.sponsorship | The work in this manuscript was supported by EU grant IST-2001-34124 (CAVIAR), Spanish grants TIC-2003-08164-C03-01 (SAMANTA) and TEC2006-11730-C03-01 (SAMANTA II) and the local administration from Andalucía grant P06-TIC-01417 (Brain System). CZR is supported by a Spanish National Research Council grant for last year degree students. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.rights | openAccess | es_ES |
dc.title | LVDS interface for AER links with burst mode operation capability | es_ES |
dc.type | comunicación de congreso | es_ES |
dc.identifier.doi | 10.1109/ISCAS.2008.4541500 | - |
dc.description.peerreviewed | Peer reviewed | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/ISCAS.2008.4541500 | es_ES |
dc.type.coar | http://purl.org/coar/resource_type/c_5794 | es_ES |
item.openairetype | comunicación de congreso | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.fulltext | With Fulltext | - |
item.languageiso639-1 | en | - |
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Fichero | Descripción | Tamaño | Formato | |
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LVDS interface.pdf | 489,38 kB | Adobe PDF | Visualizar/Abrir |
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