Using pareto-optimal fronts in the design of reconfigurable data converters

Abstract

Analog design is a bottleneck in the design of integrated circuits. A recently proposed method to cope with the complexity of analog design is the use of a multi-objective bottom- up flow, which makes use of the concept of Pareto-optimal front (POF) to capture performance trade-offs of analog components, and through which these can be exploited during top-down design of a complex (hierarchically-wise) analog circuit. In this paper, we describe a step forward and transform this technique, through a new type of front we call Multi-Mode Pareto-optimal Front, to design reconfigurable Analog-to-Digital Converters (ADCs). We demonstrate that not only design time is shortened but also that design complexity of reconfigurable circuits can be more systematically and efficiently managed.