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3D multi-layer vision architecture for surveillance and reconnaissance applications

AuthorsFöldesy, P.; Carmona-Galán, R. ; Zarandy, A.; Rekeczky, Csaba; Rodríguez-Vázquez, Ángel ; Roska, Tamás
Issue Date2009
PublisherInstitute of Electrical and Electronics Engineers
CitationEuropean Conference on Circuit Theory and Design: 185-188 (2009)
AbstractThe architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320 x 240 sensor array layer, closely coupled with a 160 x 120 mixed-signal processor array layer, a digital frame buffer layer, and an 8 x 8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS.
DescriptionTrabajo presentado al ECCTD celebrado en Antalya (Turquia) del 23 al 27 de agosto de 2009.
Publisher version (URL)http://dx.doi.org/10.1109/ECCTD.2009.5274944
Identifiersdoi: 10.1109/ECCTD.2009.5274944
isbn: 978-1-4244-3896-9
Appears in Collections:(IMSE-CNM) Libros y partes de libros
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