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Automated performance evaluation of skew-tolerant clocking schemes

AuthorsGuerrero, D.; Bellido, M. J.; Juan-Chico, J. ; Millán, Andrés; Ruiz-de-Clavijo, P.; Ostua, E.; Viejo, J.
Issue Date2006
PublisherTaylor & Francis
CitationInternational Journal of Electronics 93(12): 819-842 (2006)
AbstractIn this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master-slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS.
Identifiersdoi: 10.1080/00207210500347410
issn: 0020-7217
e-issn: 1362-3060
Appears in Collections:(IMSE-CNM) Artículos
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