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Signal sampling based transition modeling for digital gates characterization

AuthorsMillán, Alejandro; Juan-Chico, J. ; Bellido, M. J.; Ruiz-de-Clavijo, P.; Guerrero, David; Ostúa, Enrique
Issue Date2004
CitationIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 829-837 (2004)
SeriesLecture Notes in Computer Science 3254
AbstractCurrent characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%. © Springer-Verlag 2004.
Identifiersdoi: 10.1007/978-3-540-30205-6_85
isbn: 978-3-540-23095-3
Appears in Collections:(IMN-CNM) Libros y partes de libros
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