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ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

AuthorsRodríguez-Vázquez, Ángel ; Liñán-Cembrano, G. ; Carranza-González, L. ; Roca, Elisenda ; Carmona-Galán, R. ; Jiménez-Garrido, Francisco; Domínguez-Castro, R. ; Espejo-Meana, S.
Issue Date2004
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Circuits and Systems I: Regular Papers 51(5): 851-863 (2004)
AbstractToday, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3×3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.
Publisher version (URL)http://dx.doi.org/10.1109/TCSI.2004.827621
Identifiersdoi: 10.1109/TCSI.2004.827621
issn: 1549-8328
Appears in Collections:(IMSE-CNM) Artículos
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