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Title

Exploration of spatial-temporal dynamic phenomena in a 32×32-cell stored program two-layer CNN universal machine chip prototype

AuthorsPetrás, István; Rekeczky, Csaba; Roska, Tamás; Carmona-Galán, R. ; Jiménez-Garrido, Francisco; Rodríguez-Vázquez, Ángel
Issue Date2003
PublisherWorld Scientific Publishing
CitationJournal of Circuits, Systems and Computers 12(6): 691-710 (2003)
AbstractThis paper describes a full-custom mixed-signal chip that embeds digitally programmable analog parallel processing and distributed image memory on a common silicon substrate. The chip was designed and fabricated in a standard 0.5 μm CMOS technology and contains approximately 500 000 transistors. It consists of 1024 processing units arranged into a 32 × 32 grid. Each processing element contains two coupled CNN cores, thus, constituting two parallel layers of 32 × 32 nodes. The functional features of the chip are in accordance with the 2nd Order Complex Cell CNN-UM architecture. It is composed of two CNN layers with programmable inter- and intra-layer connections between cells. Other features are: cellular, spatial-invariant array architecture; randomly selectable memory of instructions; random storage and retrieval of intermediate images. The chip is capable of completing algorithmic image processing tasks controlled by the user-selected stored instructions. The internal analog circuitry is designed to operate with 7-bits equivalent accuracy. The physical implementation of a CNN containing second order cells allows real-time experiments of complex dynamics and active wave phenomena. Such well-known phenomena from the reaction-diffusion equations are traveling waves, autowaves, and spiral-waves. All of these active waves are demonstrated on-chip. Moreover this chip was specifically designed to be suitable for the computation of biologically inspired retina models. These computational experiments have been carried out in a developmental environment designed for testing and programming the analogic (analog-and-logic) programmable array processors.
DescriptionEl pdf del artículo es la versión post-print.
Publisher version (URL)http://dx.doi.org/10.1142/S0218126603001112
URIhttp://hdl.handle.net/10261/85422
DOI10.1142/S0218126603001112
Identifiersdoi: 10.1142/S0218126603001112
issn: 0218-1266
e-issn: 1793-6454
Appears in Collections:(IMN-CNM) Artículos
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