English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/85153
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:
Title

A practical floating-gate Muller-C element using vMOS threshold gates

AuthorsRodríguez-Villegas, E. ; Huertas, Gloria ; Avedillo, M. J. ; Quintana, J. M. ; Rueda, Adoración
Issue Date2001
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48(1): 102-106 (2001)
AbstractThis paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation.
DescriptionEl pdf del artículo es la versión de autor.
Publisher version (URL)http://dx.doi.org/10.1109/82.913193
URIhttp://hdl.handle.net/10261/85153
DOI10.1109/82.913193
Identifiersdoi: 10.1109/82.913193
issn: 1057-7130
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
A practical.pdf299,21 kBAdobe PDFThumbnail
View/Open
Show full item record
 

Related articles:


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.