Por favor, use este identificador para citar o enlazar a este item:
http://hdl.handle.net/10261/85044COMPARTIR / EXPORTAR:
 SHARE
BASE
|
|
| Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE | |
| Título: | vMOS-based sorters for multiplier implementations |
Autor: | Rodríguez-Villegas, E. CSIC; Avedillo, María J. CSIC ORCID; Quintana, J. M. CSIC ORCID; Huertas, Gloria CSIC ORCID; Rueda, Adoración CSIC ORCID | Fecha de publicación: | 1999 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | Proceedings of the IEEE International Symposium on Circuits and Systems 1: 338-341 (1999) | Resumen: | The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing a (8 × 8) - multiplier which uses a sorter as the main building block. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using vMOS circuits which allow to improve previous results for multipliers based on a similar architecture. | URI: | http://hdl.handle.net/10261/85044 | DOI: | 10.1109/ISCAS.1999.777872 | Identificadores: | doi: 10.1109/ISCAS.1999.777872 isbn: 0-7803-5471-0 |
| Aparece en las colecciones: | (IMSE-CNM) Libros y partes de libros |
Ficheros en este ítem:
| Fichero | Descripción | Tamaño | Formato | |
|---|---|---|---|---|
| accesoRestringido.pdf | 15,38 kB | Adobe PDF |  Visualizar/Abrir |
CORE Recommender
Page view(s)
280
checked on 24-abr-2024
Download(s)
96
checked on 24-abr-2024
Google ScholarTM
Check
Altmetric
Altmetric
NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.