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An ART1 microchip and its use in multi-ART1 systems

AuthorsSerrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé
Issue Date1997
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Neural Networks 8(5): 1184-1194 (1997)
AbstractRecently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, that chip rendered an extremely high silicon area consumption of 1 cm2, and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 μm CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip. © 1997 IEEE.
Publisher version (URL)http://dx.doi.org/10.1109/72.623219
Identifiersdoi: 10.1109/72.623219
issn: 1045-9227
e-issn: 1941-0093
Appears in Collections:(IMSE-CNM) Artículos
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