English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/84835
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE
Exportar a otros formatos:


A real-time clustering microchip neural engine

AuthorsSerrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé
Issue DateJun-1996
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Very Large Scale Integration (VLSI) Systems 4(2): 195-209 (1996)
AbstractThis paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm, but has been modified resulting in a more VLSI-friendly algorithm that allows a more efficient hardware implementation with simple circuit operators, little memory requirements, modular chip assembly capability, and higher speed figures. The chip described in this paper implements a network that can cluster 100 binary pixel input patterns into up to 18 different categories. Modular expansibility of the system is directly possible by assembling a V/spl times/M array of chips without any extra interfacing circuitry, so that the maximum number of clusters is 18/spl times/M and the maximum number of bits of the input pattern is N/spl times/100. Pattern classification and learning is performed in 1.8 /spl mu/s, which is an equivalent computing power of 4.4/spl times/10/sup 9/ connections per second plus connection-updates per second. The chip has been fabricated in a standard low cost 1.6 /spl mu/m double-metal single-poly CMOS process, has a die area of 1 cm/sup 2/, and is mounted in a 120-pin PGA package. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, and thus has a true asynchronous digital behavior. Experimental chip test results are available, obtained through digital chip test equipment. Fault tolerance at the system level operation is demonstrated through the experimental testing of faulty chips.
DescriptionEl pdf del artículo es la versión post-print.
Publisher version (URL)http://dx.doi.org/10.1109/92.502192
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
A Real-Time.pdf389,62 kBAdobe PDFThumbnail
Show full item record
Review this work

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.