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A power efficient neural spike recording channel with data bandwidth reduction

AuthorsRodríguez-Pérez, Alberto CSIC ORCID; Ruiz Amaya, Jesús; Rodríguez-Rodríguez, José Antonio; Delgado-Restituto, Manuel CSIC ORCID; Rodríguez-Vázquez, Ángel CSIC ORCID
Issue Date2011
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE International Symposium on Circuits and Systems (ISCAS): 1704-1707 (2011)
AbstractThis paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed.
Identifiersdoi: 10.1109/ISCAS.2011.5937910
isbn: 978-1-4244-9473-6
Appears in Collections:(IMSE-CNM) Libros y partes de libros

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