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Efficiency based design flow for fully-integrated class C RF power amplifiers in nanometric CMOS

AuthorsBarabino, Nicolás; Fiorelli, R. ; Silveira, Fernando
Issue Date2010
PublisherInstitute of Electrical and Electronics Engineers
CitationProceedings of IEEE International Symposium on Circuits and Systems: 2223-2226 (2010)
AbstractIn this work a design flow for class C radiofrequency (RF) power amplifiers (PA) with on-chip output networks in nanometric technologies is presented. This is a new parasitic-aware method intended to reduce time-consuming iterations which are normally required in fully-integrated designs. Unlike other methods it is based on actual transistors DC characteristics and inductors data both extracted by simulation. Starting from the output power specifications a design space map is generated showing the trade-offs between efficiency and components sizing, thus enabling the selection of the most appropriate design that satisfies the harmonic distortion requirements. As a proof of concept of the proposed method, a design example for an IEEE 802.15.4 2.4 GHz PA in a 90 nm CMOS technology is presented.
DescriptionTrabajo presentado al ISCAS celebrado en Paris del 30 de mayo al 2 de junio de 2010.
Publisher version (URL)http://dx.doi.org/10.1109/ISCAS.2010.5537207
Identifiersdoi: 10.1109/ISCAS.2010.5537207
isbn: 978-1-4244-5308-5
Appears in Collections:(IMSE-CNM) Libros y partes de libros
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