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Título: | Ultralow-power processing array for image enhancement and edge detection |
Autor: | Fernández-Berni, J. CSIC ORCID CVN; Carmona-Galán, R. CSIC ORCID ; Rodríguez-Vázquez, Ángel CSIC ORCID | Fecha de publicación: | 2012 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | IEEE Transactions on Circuits and Systems II: Express Briefs 59(11): 751-755 (2012) | Resumen: | This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be turned into anisotropic by a very simple voltage comparator between neighboring nodes whose output controls the gate of the elementary MOS resistor. Anisotropic diffusion enables image enhancement by removing noise and small local variations while preserving edges. A binary edge image can also be attained by combining the output of the voltage comparators. In addition to these processing capabilities, the simulations have confirmed the robustness of the array against process variations and mismatch. The power consumption extrapolated for VGA-resolution array processing images at 30 fps is 570 μW. | Descripción: | El pdf del artículo es la versión post-print. | Versión del editor: | http://dx.doi.org/10.1109/TCSII.2012.2228394 | URI: | http://hdl.handle.net/10261/83669 | DOI: | 10.1109/TCSII.2012.2228394 | Identificadores: | doi: 10.1109/TCSII.2012.2228394 issn: 1549-7747 e-issn: 1558-3791 |
Aparece en las colecciones: | (IMSE-CNM) Artículos |
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ultra_low.pdf | 594,6 kB | Adobe PDF | Visualizar/Abrir |
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