English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/83543
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:

DC FieldValueLanguage
dc.contributor.authorSuárez, Marta-
dc.contributor.authorBrea, V. M.-
dc.contributor.authorFernández-Berni, J.-
dc.contributor.authorCarmona-Galán, R.-
dc.contributor.authorLiñán-Cembrano, G.-
dc.contributor.authorLiñán-Cembrano, G.-
dc.contributor.authorRodríguez-Vázquez, Ángel-
dc.date.accessioned2013-10-08T09:00:28Z-
dc.date.available2013-10-08T09:00:28Z-
dc.date.issued2012-
dc.identifierdoi: 10.1109/JETCAS.2012.2223552-
dc.identifierissn: 2156-3357-
dc.identifier.citationIEEE Journal on Emerging and Selected Topics in Circuits and Systems 2(4): 723-736 (2012)-
dc.identifier.urihttp://hdl.handle.net/10261/83543-
dc.descriptionEl pdf del artículo es la versión post-print.-
dc.description.abstractThis paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.-
dc.description.sponsorshipThis work has been funded by Xunta de Galicia (SPAIN) through project 10PXIB206037PR, MICINN (SPAIN) through projects TEC2009-12686, IPT-2011-1625-430000, and by ONR through Project N000141110312.-
dc.language.isoeng-
dc.relation.isversionofPostprint-
dc.rightsopenAccess-
dc.titleCMOS-3D smart imager architectures for feature detection-
dc.typeartículo-
dc.identifier.doi10.1109/JETCAS.2012.2223552-
dc.relation.publisherversionhttp://dx.doi.org/10.1109/JETCAS.2012.2223552-
dc.date.updated2013-10-08T09:00:29Z-
dc.description.versionPeer Reviewed-
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
cmos3d.pdf1,12 MBAdobe PDFThumbnail
View/Open
Show simple item record
 

Related articles:


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.