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CMOS-3D smart imager architectures for feature detection

AuthorsSuárez, Marta CSIC ORCID; Brea, V. M.; Fernández-Berni, J. CSIC ORCID CVN; Carmona-Galán, R. CSIC ORCID ; Liñán-Cembrano, G. CSIC ORCID ; Liñán-Cembrano, G. CSIC ORCID ; Rodríguez-Vázquez, Ángel CSIC ORCID
Issue Date2012
CitationIEEE Journal on Emerging and Selected Topics in Circuits and Systems 2(4): 723-736 (2012)
AbstractThis paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.
DescriptionEl pdf del artículo es la versión post-print.
Publisher version (URL)
Identifiersdoi: 10.1109/JETCAS.2012.2223552
issn: 2156-3357
Appears in Collections:(IMSE-CNM) Artículos

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