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LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies

AuthorsFiorelli, R. ; Peralías, E. ; Silveira, Fernando
Issue Date2011
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Microwave Theory and Techniques 59(7): 1822-1831 (2011)
AbstractIn this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier. © 2011 IEEE.
DescriptionEl pdf del artículo es la versión pre-print.
Publisher version (URL)http://dx.doi.org/10.1109/TMTT.2011.2132735
Identifiersdoi: 10.1109/TMTT.2011.2132735
issn: 0018-9480
Appears in Collections:(IMSE-CNM) Artículos
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