English   español  
Por favor, use este identificador para citar o enlazar a este item: http://hdl.handle.net/10261/7823
Compartir / Impacto:
Estadísticas
Add this article to your Mendeley library MendeleyBASE
Citado 62 veces en Web of Knowledge®  |  Ver citas en Google académico
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar otros formatos: Exportar EndNote (RIS)Exportar EndNote (RIS)Exportar EndNote (RIS)
Título : A neuromorphic cortical-layer microchip for spike-based event processing vision systems
Autor : Serrano-Gotarredona, Rafael; Serrano-Gotarredona, Teresa ; Acosta, Antonio José ; Linares-Barranco, Bernabé
Palabras clave : 2-D convolutions
Address-event representation (AER)
Bio-inspired systems
High-speed signal processing
MOS transistor mismatch
Spike-based processing
Subthreshold circuits
VLSI
Fecha de publicación : 16-oct-2006
Citación : IEEE Transactions on Circuits and Systems I: Regular Papers 53(12): 2548-2566 (2006)
Resumen: We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 32 pixels. The convolution processor operates on a pixel array of size 32 32, but can process an input space of up to 128 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second.
Versión del editor: http://dx.doi.org/10.1109/TCSI.2006.883843
URI : http://hdl.handle.net/10261/7823
DOI: 10.1109/TCSI.2006.883843
ISSN: 1549-8328
Aparece en las colecciones: (IMS-CNM) Artículos
Ficheros en este ítem:
Fichero Descripción Tamaño Formato  
neuromorphic cortical.pdf4,2 MBAdobe PDFVista previa
Visualizar/Abrir
Mostrar el registro completo
 



NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.