English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/52639
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:
Title

1 V CMOS subthreshold log domain PDM

AuthorsSerra-Graells, Francesc ; Huertas-Díaz, J. L.
KeywordsLow voltage
CMOS
Subthreshold
Log
PDM
Issue DateMar-2003
PublisherSpringer
CitationAnalog Integrated Circuits and Signal Processing 34(3): 183-187 (2003)
AbstractA new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.
Publisher version (URL)http://dx.doi.org/10.1023/A:1022545414777
URIhttp://hdl.handle.net/10261/52639
DOI10.1023/A:1022545414777
ISSN0925-1030
E-ISSN1573-1979
Appears in Collections:(IMB-CNM) Artículos
(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
alog990-02-postprint.pdf296,43 kBAdobe PDFThumbnail
View/Open
Show full item record
Review this work
 


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.