English   español  
Por favor, use este identificador para citar o enlazar a este item: http://hdl.handle.net/10261/48219
Compartir / Impacto:
Estadísticas
Add this article to your Mendeley library MendeleyBASE
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Título

Low-power die-level process variation and temperature monitors for yield analysis and optimization in deep-submicron CMOS

AutorZjajo, Amir; Barragán, Manuel J. ; Pineda de Gyvez, José
Palabras claveAnalog test
Process variation monitoring
Temperature monitors
Yield enhancement
Fecha de publicación6-feb-2012
EditorInstitute of Electrical and Electronics Engineers
CitaciónIEEE Transactions on Instrumentation and Measurement 61(8): 2212-2221 (2012)
ResumenThis paper reports design, efficiency, and measure- ment results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation–maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to- digital converter fabricated in standard single poly six-metal 90-nm CMOS.
Versión del editorhttp://dx.doi.org/10.1109/TIM.2012.2184195
URIhttp://hdl.handle.net/10261/48219
DOI10.1109/TIM.2012.2184195
ISSN0018-9456
Aparece en las colecciones: (IMSE-CNM) Artículos
Ficheros en este ítem:
Fichero Descripción Tamaño Formato  
accesoRestringido.pdf15,38 kBAdobe PDFVista previa
Visualizar/Abrir
Mostrar el registro completo
 

Artículos relacionados:


NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.