English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/45088
logo share SHARE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE
Exportar a otros formatos:

DC FieldValueLanguage
dc.contributor.authorBarragán, Manuel J.-
dc.contributor.authorFiorelli, R.-
dc.contributor.authorLeger, Gildas-
dc.contributor.authorRueda, Adoración-
dc.contributor.authorHuertas-Díaz, J. L.-
dc.identifier.citation20th Asian Test Symposium (ATS): 359-364 (2011)es_ES
dc.descriptionTrabajo presentado al "20 Asina Test Symposium" celebrado en Nueva Delhi (India) del 20 al 23 de Noviembre del 2011.-- Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the products or services of CSIC Spanish National Research Council, Digital.CSIC. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.-
dc.description.abstractThis work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning mod- els, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post- layout simulation results are provided to verify the functionality of the approach. Copyright © 2011 IEEE.es_ES
dc.description.sponsorshipThis work has been partially funded by a CSIC JAE-Doc contract (cofinanced by FSE), a Spanish MAE-AECID grant and projects: SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2010-55, cofinanced with FEDER program), Auto-calibración y auto-test en circuitos analógicos, mixtos y de radio frecuencia (Andalusian Government project P09-TIC-5386, cofinanced with FEDER program), and Catrene project TOETS (CT 302).-
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.titleImproving the accuracy of RF alternate test using multi-VDD conditions: application to envelope-based test of LNAses_ES
dc.typecomunicación de congresoes_ES
dc.description.peerreviewedPeer reviewedes_ES
Appears in Collections:(IMSE-CNM) Libros y partes de libros
Files in This Item:
File Description SizeFormat 
RF alternate.pdf1,12 MBAdobe PDFThumbnail
Show simple item record

Related articles:

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.