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A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

AuthorsTortosa, Ramón CSIC; Aceituno, Antonio; Rosa, José M. de la CSIC ORCID; Rodríguez-Vázquez, Ángel CSIC ORCID; Fernández, Francisco V. CSIC ORCID
KeywordsContinuous-Time Circuits
Sigma-Delta Modulators
Issue DateMay-2007
PublisherInstitute of Electrical and Electronics Engineers
CitationR. Tortosa-Navas,A. Aceituno, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator". Proceeding of the 2007 International Symposium on Circuits and Systems (ISCAS), New Orleans, May 2007.
AbstractThis paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.
Appears in Collections:(IMSE-CNM) Comunicaciones congresos

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