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Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator

AuthorsTortosa, Ramón ; Aceituno, Antonio; Rosa, José M. de la ; Fernández, Francisco V. ; Rodríguez-Vázquez, Ángel
KeywordsContinuous-Time Circuits
Sigma-Delta Modulators
Issue DateDec-2006
PublisherInstitute of Electrical and Electronics Engineers
CitationR. Tortosa, A. Aceituno, J. M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: "Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator". Proc. of the 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Niza, December 2006.
AbstractThis paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
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