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Adaptive CMOS Circuits for 4G Wireless Networks
|Autor:||Rosa, José M. de la ; Ismail, Mohammed|
|Palabras clave:||Adaptive Analog/RF Circuits|
4G Wireless Networks
|Fecha de publicación:||ago-2007|
|Citación:||José M. de la Rosa and Mohammed Ismail: "Adaptive CMOS Circuits for 4G Wireless Networks". Tutorial at ECCTD 2007|
|Resumen:||The extraordinary growth of wireless communication technologies has prompted the emergence of a large number of new applications and standards. These new standards -like WMAN or UWB- are complementing the existing ones -such as GSM, UMTS or WLAN- and it is forecasted that the fourth generation (4G) of wireless terminals will make the convergence of services provided by cellular phones, satellite, long-range and short-range connectivity possible, giving rise to the so-called always-best-connected systems. The implementation of these systems in future handheld wireless devices will require low power low cost multi-standard multi-band chipsets, capable to operate over the different co-existing communication protocols, signal conditions, battery status, etc. The efficient implementation of these chipsets demands for reconfigurable building blocks that can adapt to the large number specifications with minimum power dissipation and at the lowest cost.|
Nanometer CMOS processes are expected to be the base technologies to develop this new generation of RF transceivers, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. Fuelled by the technology evolution, the trend is to move the digitizing component as close as possible to the antenna, whereas the role of analog/RF circuits consists of implementing the necessary signal conditioning and data conversion interface. However, the integration in standard CMOS of increasingly complex analog/RF parts, with stringent demands on power consumption and cost as the two main differentiators, imposes a number of challenges and trade-offs that make their design a key issue to guarantee the quality of service of future beyond-3G (B3G) wireless devices.
These challenges will be addressed in this tutorial through a comprehensive description of the state-of-the-art architectures, building-blocks, design trade-offs and practical considerations of reconfigurable CMOS RF/analog circuits for emerging B3G systems. The tutorial is divided into two lectures. The first presentation deals with radio design IPs whereas the second presentation focuses on data converters. These presentations will highlight both the trends and the opportunities for innovation in this area. A number of topics will be covered including: system-planning strategies, architecture- vs. circuit-level reconfiguration techniques, first-pass-silicon radio transceiver design in nanometer CMOS, robustness-vs.-reconfigurability trade-offs, low-voltage and low-power circuit techniques. Finally, examples from test chips will be presented.
|Versión del editor:||http://ecctd07.imse.cnm.es/t.html|
|Aparece en las colecciones:||(IMSE-CNM) Cursos-Material didáctico|
Ficheros en este ítem:
|ECCTD07_TutorialJrosa.pdf||7,03 MB||Adobe PDF|
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