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|Authors:||Domínguez-Castro, R. ; Rodríguez-Vázquez, Ángel ; Rosa, José M. de la ; Delgado-Restituto, Manuel ; Medeiro, Fernando|
|Abstract:||This chapter first presents an overview of CMOS voltage comparator architectures and circuits. Starting from the identification of the comparator behavior, Section 2 introduces several comparator architectures and circuits. Then, Section 3 assumes these topologies, characterizes high-level attributes, such as static gain, unitary time constant, etc., and analyzes the trade-off for each architecture. Such analysis provides a basis for comparison among architectures. These previous sections of the chapter neglect the influence of circuit dissymmetries. Dissymmetries are covered in Section 4; and new comparator topologies are presented to overcome the offset caused by dissymmetries. Related high-level trade-offs for these topologies are also studied in this section.|
|Publisher version (URL):||http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4020-7546-9|
|Appears in Collections:||(IMSE-CNM) Libros y partes de libros|
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