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dc.contributor.authorMedeiro, Fernando-
dc.contributor.authorPérez-Verdú, Belén-
dc.contributor.authorRosa, José M. de la-
dc.contributor.authorRodríguez-Vázquez, Ángel-
dc.date.accessioned2008-04-25T10:40:04Z-
dc.date.available2008-04-25T10:40:04Z-
dc.date.issued1997-
dc.identifier.citationJournal Circuit Theory Applications 25(5): 319-334 (1997)en_US
dc.identifier.issn0098-9886-
dc.identifier.urihttp://hdl.handle.net/10261/3744-
dc.descriptionEl pdf del artículo es la versión post-print.-
dc.description.abstractThis paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16.4 bit at a digital output rate of 9.6 kHz with a power consumption of 1.7 mW. It yields a value of Power(W)/[2^resolution(bit) * Outpur rate(Hz)] which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies.en_US
dc.format.extent1635147 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoengen_US
dc.publisherWiley-Blackwellen_US
dc.relation.isversionofPostprint-
dc.rightsopenAccessen_US
dc.subjectMixed-signal circuitsen_US
dc.subjectData conversionen_US
dc.subjectΣΔMen_US
dc.subjectOptimized designen_US
dc.subjectCAD toolsen_US
dc.titleUsing CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technologyen_US
dc.typeArtículoen_US
dc.identifier.doi10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U-
dc.description.peerreviewedPeer revieweden_US
dc.relation.publisherversionhttp://dx.doi.org/10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U-
dc.identifier.e-issn1097-007X-
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