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dc.contributor.authorMedeiro, Fernando-
dc.contributor.authorPérez-Verdú, Belén-
dc.contributor.authorRosa, José M. de la-
dc.contributor.authorRodríguez-Vázquez, Ángel-
dc.date.accessioned2008-04-24T14:03:02Z-
dc.date.available2008-04-24T14:03:02Z-
dc.date.issued1998-10-01-
dc.identifier.citationIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications: 1041-1051 (1998)en_US
dc.identifier.issn1057-7122-
dc.identifier.urihttp://hdl.handle.net/10261/3729-
dc.description.abstractFourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires careful consideration of their performance degradations due to the hardware nonidealities. This paper presents a comparative study of the influence of finite op-amp gain and capacitor mismatch on the performance of fourth-order cascade ΣΔ modulators realized by means of switched-capacitor circuits. It considers single-bit and multibit quantizers and draws a number of comparative remarks validated by time-domain behavioral simulations.en_US
dc.description.sponsorshipThis work was supported in part by the CEE ESPRIT Program under Project #8795 (AMFIS).en_US
dc.format.extent397876 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoengen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.rightsopenAccessen_US
dc.subjectAnalog-digital conversionen_US
dc.subjectΣΔ modulatorsen_US
dc.subjectSwitched-capacitor circuitsen_US
dc.titleFourth-order cascade SC ΣΔ modulators: a comparative studyen_US
dc.typeartículoen_US
dc.identifier.doi10.1109/81.728858-
dc.description.peerreviewedPeer revieweden_US
dc.relation.publisherversionhttp://dx.doi.org/10.1109/81.728858-
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