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Characterization of a Low-Cost FPGA-based Time-to-Digital Converter with Maximized Readout Speed

AuthorsParsakordasiabi, Mojtaba; Vornicu, Ion; Rodríguez-Vázquez, Ángel ; Carmona-Galán, R.
KeywordsField-programmable gate array (FPGA)
Time-to-digital converter (TDC)
Readout speed, Multichannel TDCs
Time-of-flight (ToF)
Issue Date2021
CitationParsakordasiabi, Mojtaba; Vornicu, Ion; Rodríguez-Vázquez, Ángel; Carmona-Galán, Ricardo; 2021; Characterization of a Low-Cost FPGA-based Time-to-Digital Converter with Maximized Readout Speed [Dataset], 2021
AbstractThis dataset includes: (i) code density test results obtained from 116272 collected samples; (ii) Differential and integral nonlinearities (DNL and INL) of uncalibrated and calibrated outputs calculated from estimated widths of delay elements; and (iii) Graphs of measured bin widths, bin width distribution, comparison of ideal, uncalibrated, and calibrated transfer functions, uncalibrated DNL and INL, and calibrated DNL and INL.
DescriptionThis dataset reports the specifications of a low-cost FPGA-based TDC whose readout speed is maximized. The evaluated TDC is composed of a toggling input stage to shape the hit signal and maximize the readout speed, a coarse counter to count the number of clocks between start and stop signals, a tuned tapped delay line to achieve high resolution, a dual-mode counter-based encoder to convert the output of the delay line to a binary number, a controller to determine the encoding mode, and a bin-width calibration to improve the TDC performance. To measure the exact bin widths and calculate the DNL and INL of the TDC, the code density test that is a statistical estimation approach, is hired.
Appears in Collections:(IMSE-CNM) Conjuntos de datos
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