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dc.contributor.authorParsakordasiabi, Mojtabaes_ES
dc.contributor.authorVornicu, Iones_ES
dc.contributor.authorRodríguez-Vázquez, Ángeles_ES
dc.contributor.authorCarmona-Galán, R.es_ES
dc.date.accessioned2021-02-01T08:12:09Z-
dc.date.available2021-02-01T08:12:09Z-
dc.date.issued2021-
dc.identifier.citationSensors 21(1): 308 (2021)es_ES
dc.identifier.urihttp://hdl.handle.net/10261/228099-
dc.description© 2021 by the authors.-
dc.description.abstractIn this paper, we present a proposed field programmable gate array (FPGA)-based timeto- digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [0.953, 1.185] LSB, and an integral non-linearity (INL) within [2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.es_ES
dc.description.sponsorshipThis work was supported by EU H2020 MSCA through Project ACHIEVE-ITN (Grant No 765866), by the Spanish MINECO and European Region Development Fund (ERDF/FEDER) through Project RTI2018-097088-B-C31, and by the US Office of Naval Research through Grant No. N00014-19-1-2156.-
dc.language.isoenges_ES
dc.publisherMultidisciplinary Digital Publishing Institutees_ES
dc.relationinfo:eu-repo/grantAgreement/EC/H2020/765866-
dc.relationRTI2018-097088-B-C31RTI2018-097088-B-C31-
dc.relationRTI2018-097088-B-C31/AEI/10.13039/501100011033-
dc.relation.isversionofPublisher's versiones_ES
dc.rightsopenAccesses_ES
dc.subjectField programmable gate array (FPGA)es_ES
dc.subjectTapped-delay-line (TDL)es_ES
dc.subjectThermometer-to-binary (T2B) encoderes_ES
dc.subjectMultichannel TDCses_ES
dc.subjectTime-to-digital converter (TDC)es_ES
dc.subjectTime-of-flight (ToF)es_ES
dc.subjectSinglephoton avalanche diode (SPAD)es_ES
dc.titleA Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGAes_ES
dc.typeartículoes_ES
dc.identifier.doihttp://dx.doi.org/10.3390/s21010308-
dc.description.peerreviewedPeer reviewedes_ES
dc.relation.publisherversionhttps://doi.org/10.3390/s21010308es_ES
dc.identifier.e-issn1424-8220-
dc.rights.licensehttps://creativecommons.org/licenses/by-nc-nd/4.0/es_ES
dc.contributor.funderEuropean Commission-
dc.contributor.funderMinisterio de Ciencia, Innovación y Universidades (España)-
dc.contributor.funderAgencia Estatal de Investigación (España)-
dc.relation.csices_ES
oprm.item.hasRevisionno ko 0 false*
dc.identifier.funderhttp://dx.doi.org/10.13039/501100011033es_ES
dc.identifier.funderhttp://dx.doi.org/10.13039/501100000780es_ES
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