A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Abstract

In this paper, we present a proposed field programmable gate array (FPGA)-based timeto- digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [0.953, 1.185] LSB, and an integral non-linearity (INL) within [2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.