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Título: | PhD Forum: Impact of CNNs Pooling Layer Implementation on FPGAs Accelerator Design |
Autor: | Muñío-Gracia, A. CSIC; Fernández-Berni, J. CSIC ORCID CVN; Carmona-Galán, R. CSIC ORCID ; Rodríguez-Vázquez, Ángel CSIC ORCID | Palabras clave: | Convolutional neural networks FPGA Hardware acceleration |
Fecha de publicación: | 2019 | Editor: | Association for Computing Machinery | Citación: | ICDSC 2019 Proceedings of the 13th International Conference on Distributed Smart Cameras Article No. 28 (2019) | Resumen: | Convolutional Neural Networks have demonstrated their competence in extracting information from data, especially in the field of computer vision. Their computational complexity prompts for hardware acceleration. The challenge in the design of hardware accelerators for CNNs is providing a sustained throughput with low power consumption, for what FPGAs have captured community attention. In CNNs pooling layers are introduced to reduce model spatial dimensions. This work explores the influence of pooling layers modification in some state-of-the-art CNNs, namely AlexNet and SqueezeNet. The objective is to optimize hardware resources utilization without negative impact on inference accuracy | Descripción: | Proceeding ICDSC 2019 Proceedings of the 13th International Conference on Distributed Smart Cameras Article No. 28. Trento, Italy — September 09 - 11, 2019 | Versión del editor: | https://doi.org/10.1145/3349801.3357130 | URI: | http://hdl.handle.net/10261/194357 | DOI: | 10.1145/3349801.3357130 |
Aparece en las colecciones: | (IMSE-CNM) Comunicaciones congresos |
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