Por favor, use este identificador para citar o enlazar a este item:
http://hdl.handle.net/10261/160575
COMPARTIR / EXPORTAR:
SHARE CORE BASE | |
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE | |
Campo DC | Valor | Lengua/Idioma |
---|---|---|
dc.contributor.author | Avedillo, María J. | es_ES |
dc.contributor.author | Núñez, Juan | es_ES |
dc.date.accessioned | 2018-02-13T12:45:38Z | - |
dc.date.available | 2018-02-13T12:45:38Z | - |
dc.date.issued | 2017-09-05 | - |
dc.identifier.citation | International Journal of Circuit Theory and Applications, in press. | es_ES |
dc.identifier.uri | http://hdl.handle.net/10261/160575 | - |
dc.description.abstract | Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Wiley-Blackwell | es_ES |
dc.relation.isversionof | Postprint | es_ES |
dc.rights | openAccess | en_EN |
dc.title | Impact of the RT-level architecture on the power performance of tunnel transistor circuits | es_ES |
dc.type | artículo | es_ES |
dc.identifier.doi | 10.1002/cta.2398 | - |
dc.description.peerreviewed | Peer reviewed | es_ES |
dc.relation.publisherversion | htpp://dx.doi.org/10.1002/cta.2398 | es_ES |
dc.embargo.terms | 2018-08-04 | es_ES |
dc.relation.csic | Sí | es_ES |
oprm.item.hasRevision | no ko 0 false | * |
dc.type.coar | http://purl.org/coar/resource_type/c_6501 | es_ES |
item.openairetype | artículo | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.fulltext | With Fulltext | - |
item.languageiso639-1 | en | - |
Aparece en las colecciones: | (IMSE-CNM) Artículos |
Ficheros en este ítem:
Fichero | Descripción | Tamaño | Formato | |
---|---|---|---|---|
IJCTA_avedillo_nunez_review.pdf | 854,38 kB | Adobe PDF | Visualizar/Abrir |
CORE Recommender
SCOPUSTM
Citations
2
checked on 16-abr-2024
WEB OF SCIENCETM
Citations
2
checked on 24-feb-2024
Page view(s)
235
checked on 22-abr-2024
Download(s)
313
checked on 22-abr-2024
Google ScholarTM
Check
Altmetric
Altmetric
NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.