English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/160006
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE
Exportar a otros formatos:

DC FieldValueLanguage
dc.contributor.authorPaolieri, Marco-
dc.contributor.authorQuiñones, Eduardo-
dc.contributor.authorCazorla, Francisco J.-
dc.contributor.authorValero, Mateo-
dc.date.accessioned2018-02-01T11:26:52Z-
dc.date.available2018-02-01T11:26:52Z-
dc.date.issued2009-
dc.identifierdoi: 10.1109/LES.2010.2041634-
dc.identifierissn: 1943-0663-
dc.identifier.citationIEEE Embedded Systems Letters 1: 86- 90 (2009)-
dc.identifier.urihttp://hdl.handle.net/10261/160006-
dc.description.abstractMulticore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations. © 2009 IEEE.-
dc.description.sponsorshipThis work has been supported by the Ministry of Science and Technology of Spain under contract TIN-2007-60625, by the HiPEAC European Network of Excellence, and by the MERASA STREP-FP7 European Project under the Grant 216415. Marco Paolieri is supported by the Catalan Ministry for Innovation, Universities and Enterprise of the Catalan Government and European Social Funds.-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.rightsclosedAccess-
dc.subjectWorst case execution time (WCET)-
dc.subjectCMP-
dc.subjectDDRx SDRAM-
dc.subjectHard real-time-
dc.subjectMemory controller-
dc.titleAn analyzable memory controller for hard real-time CMPs-
dc.typeartículo-
dc.date.updated2018-02-01T11:26:52Z-
dc.description.versionPeer Reviewed-
dc.language.rfc3066eng-
dc.contributor.funderEuropean Commission-
dc.contributor.funderMinisterio de Ciencia y Tecnología (España)-
dc.contributor.funderGeneralitat de Catalunya-
dc.relation.csic-
dc.identifier.funderhttp://dx.doi.org/10.13039/501100002809es_ES
dc.identifier.funderhttp://dx.doi.org/10.13039/501100006280es_ES
dc.identifier.funderhttp://dx.doi.org/10.13039/501100000780es_ES
Appears in Collections:(IIIA) Artículos
Files in This Item:
File Description SizeFormat 
accesoRestringido.pdf15,38 kBAdobe PDFThumbnail
View/Open
Show simple item record
 


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.