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An analyzable memory controller for hard real-time CMPs

AuthorsPaolieri, Marco; Quiñones, Eduardo; Cazorla, Francisco J. ; Valero, Mateo
KeywordsWorst case execution time (WCET)
Hard real-time
Memory controller
Issue Date2009
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Embedded Systems Letters 1: 86- 90 (2009)
AbstractMulticore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations. © 2009 IEEE.
Identifiersdoi: 10.1109/LES.2010.2041634
issn: 1943-0663
Appears in Collections:(IIIA) Artículos
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