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A Hybrid CMOS-Memristor Neuromorphic Synapse

AutorAzghadi, Mostafa, R.; Linares-Barranco, Bernabé ; Abbott, Derek; Leong, Philip H.W.
Palabras claveSynaptic Plasticity
Fecha de publicación2017
EditorInstitute of Electrical and Electronics Engineers
CitaciónIEEE Transactions on Biomedical Circuits and Systems 11: 434- 445 (2017)
ResumenAlthough data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre-and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as 600μm in a 0.35μm process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.
Identificadoresdoi: 10.1109/TBCAS.2016.2618351
issn: 1932-4545
Aparece en las colecciones: (IMSE-CNM) Artículos
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