English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/155904
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE
Exportar a otros formatos:


Improving speed of tunnel FETs logic circuits

AuthorsAvedillo, M. J. ; Núñez, Juan
Issue Date2015
PublisherInstitute of Electrical and Electronics Engineers
CitationElectronics Letters, 51(21): 1702-1704 (2015)
AbstractTunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital TFETs circuits leading to delay degradation. In this paper, we propose a minor modification of the complementary gate topology to avoid the bootstrapping problem and show its impact on speed at the circuit level. Speed improvements up to 33% have been obtained for 8-bit Ripple Carry Adders when implemented with our solution.
Publisher version (URL)https://doi.org/10.1049/el.2015.2416
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
EL_submitted.pdf125,98 kBAdobe PDFThumbnail
Show full item record
Review this work

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.