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Title

Improving speed of tunnel FETs logic circuits

AuthorsAvedillo, M. J. ; Núñez, Juan
Issue Date2015
PublisherInstitute of Electrical and Electronics Engineers
CitationElectronics Letters, 51(21): 1702-1704 (2015)
AbstractTunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital TFETs circuits leading to delay degradation. In this paper, we propose a minor modification of the complementary gate topology to avoid the bootstrapping problem and show its impact on speed at the circuit level. Speed improvements up to 33% have been obtained for 8-bit Ripple Carry Adders when implemented with our solution.
Publisher version (URL)https://doi.org/10.1049/el.2015.2416
URIhttp://hdl.handle.net/10261/155904
DOIhttp://dx.doi.org/10.1049/el.2015.2416
Appears in Collections:(IMSE-CNM) Artículos
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