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Title

A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics

AuthorsSoler, Joan Ramon ; Manyà, Felip
KeywordsMany-Valued logic
Lukasiewicz logic
SMT
Satisfiability
Issue Date19-May-2016
PublisherInstitute of Electrical and Electronics Engineers. Computer Group
Citation2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL), pp. 270-275
AbstractWe define a new bit-vector approach for reducing the satisfiability problem of any finitely-valued logic to SAT. Our approach consists of encoding the finitely-valued logic and the formula under consideration as an SMT program under the logic of quantifier-free uninterpreted functions and bit vectors (QF\_UFBV), and then automatically derive a SAT instance using flattening techniques and efficient CNF conversion algorithms. Moreover, we report on an experimental investigation that demonstrates that the proposed approach is competitive.
URIhttp://hdl.handle.net/10261/155762
DOIhttp://dx.doi.org/10.1109/ISMVL.2016.47
Identifiersdoi: 10.1109/ISMVL.2016.47
issn: 0195623X
Appears in Collections:(IIIA) Comunicaciones congresos
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