English   español  
Por favor, use este identificador para citar o enlazar a este item: http://hdl.handle.net/10261/155762
COMPARTIR / IMPACTO:
Estadísticas
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:
Título

A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics

AutorSoler, Joan Ramon ; Manyà, Felip
Palabras claveMany-Valued logic
Lukasiewicz logic
SMT
Satisfiability
Fecha de publicación19-may-2016
EditorInstitute of Electrical and Electronics Engineers. Computer Group
Citación2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL), pp. 270-275
ResumenWe define a new bit-vector approach for reducing the satisfiability problem of any finitely-valued logic to SAT. Our approach consists of encoding the finitely-valued logic and the formula under consideration as an SMT program under the logic of quantifier-free uninterpreted functions and bit vectors (QF\_UFBV), and then automatically derive a SAT instance using flattening techniques and efficient CNF conversion algorithms. Moreover, we report on an experimental investigation that demonstrates that the proposed approach is competitive.
URIhttp://hdl.handle.net/10261/155762
DOI10.1109/ISMVL.2016.47
Identificadoresdoi: 10.1109/ISMVL.2016.47
issn: 0195623X
Aparece en las colecciones: (IIIA) Comunicaciones congresos
Ficheros en este ítem:
Fichero Descripción Tamaño Formato  
accesoRestringido.pdf15,38 kBAdobe PDFVista previa
Visualizar/Abrir
Mostrar el registro completo
 


NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.