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Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core

AuthorsMarkovic, Nikola; Nemirovsky, Daniel; Unsal, Osman; Valero, Mateo; Crista, Adrian
KeywordsHW/SW thread scheduling
Multi-threaded applications
Asymmetric chip multiprocessor (ACMP)
Issue Date2015
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Computer Architecture Letters 14: 160- 163 (2015)
AbstractAs thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. As more and more applications become multi-threaded we expect to find a growing number of threads executing on a machine. As a consequence, the operating system will require increasingly larger amounts of CPU time to schedule these threads efficiently. Instead of perpetuating the trend of performing more complex thread scheduling in the operating system, we propose a scheduling mechanism that can be efficiently implemented in hardware as well. Our approach of identifying multi-threaded application bottlenecks such as thread synchronization sections complements the Fairness-aware Scheduler method. It achieves an average speed up of 11.5 percent (geometric mean) compared to the state-of-the-art Fairness-aware Scheduler.
Identifiersdoi: 10.1109/LCA.2014.2357805
issn: 1556-6056
Appears in Collections:(IIIA) Artículos
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