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dc.contributor.authorAliaga, Jose I.-
dc.contributor.authorBadia, Rosa M.-
dc.contributor.authorBarreda, Maria-
dc.contributor.authorBollhöfer, Matthias-
dc.contributor.authorDufrechou, Ernesto-
dc.contributor.authorEzzatti, Pablo-
dc.contributor.authorQuintana-Orti, Enrique S.-
dc.date.accessioned2016-10-26T15:21:50Z-
dc.date.available2016-10-26T15:21:50Z-
dc.date.issued2016-
dc.identifierdoi: 10.1016/j.parco.2015.12.004-
dc.identifierissn: 0167-8191-
dc.identifier.citationParallel Computing 54: 97- 107 (2016)-
dc.identifier.urihttp://hdl.handle.net/10261/139427-
dc.description.abstractWe present specialized implementations of the preconditioned iterative linear system solver in ILUPACK for Non-Uniform Memory Access (NUMA) platforms and many-core hardware co-processors based on the Intel Xeon Phi and graphics accelerators. For the conventional x86 architectures, our approach exploits task parallelism via the OmpSs runtime as well as a message-passing implementation based on MPI, respectively yielding a dynamic and static schedule of the work to the cores, with different numeric semantics to those of the sequential ILUPACK. For the graphics processor we exploit data parallelism by off-loading the computationally expensive kernels to the accelerator while keeping the numeric semantics of the sequential case.-
dc.description.sponsorshipThe authors from the Universitat Jaume I were supported by the projects EU FP7 318793 (Exa2Green), TIN2011-23283 of the Ministerio de Economía y Competitividad (MINECO) and EU FEDER, and P11B2013-20 of the Fundació Caixa Castelló-Bancaixa and UJI. Rosa M. Badia was supported by project TIN2012-34557 of MINECO and EU FEDER, and by the Generalitat de Catalunya (contract 2009-SGR-980). María Barreda was supported by the FPU program of the Ministerio de Educación, Cultura y Deporte. We thank Francisco D. Igual, from Universidad Complutense de Madrid (Spain), for his help with the Intel Xeon Phi.-
dc.publisherElsevier-
dc.relationinfo:eu-repo/grantAgreement/EC/FP7/318793-
dc.rightsclosedAccess-
dc.subjectSparse linear systems-
dc.subjectTask and data parallelism-
dc.subjectReconditioned Conjugate Gradient solver-
dc.subjectMulti-core processors-
dc.subjectIntel Xeon Phi-
dc.subjectGraphics processing units (GPUs)-
dc.titleExploiting task and data parallelism in ILUPACK's preconditioned CG solver on NUMA architectures and many-core accelerators-
dc.typeartículo-
dc.identifier.doi10.1016/j.parco.2015.12.004-
dc.date.updated2016-10-26T15:21:51Z-
dc.description.versionPeer Reviewed-
dc.language.rfc3066eng-
dc.contributor.funderMinisterio de Educación, Cultura y Deporte (España)-
dc.contributor.funderMinisterio de Economía y Competitividad (España)-
dc.contributor.funderEuropean Commission-
dc.contributor.funderGeneralitat de Catalunya-
dc.relation.csic-
dc.identifier.funderhttp://dx.doi.org/10.13039/501100003176es_ES
dc.identifier.funderhttp://dx.doi.org/10.13039/501100003329es_ES
dc.identifier.funderhttp://dx.doi.org/10.13039/501100000780es_ES
dc.identifier.funderhttp://dx.doi.org/10.13039/501100002809es_ES
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