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Título

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

AutorNúñez, Juan ; Ginés, A. J. ; Peralías, E. ; Rueda, Adoración
Palabras claveClock recovery
Ultra-low jitter
Design methodology
High-speed high-resolution ADCs
Pipeline ADCs
Fecha de publicación2016
EditorSpringer
CitaciónAnalog Integrated Circuits and Signal Processing, 2016
ResumenThis paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm). Post-layout simulation results for a case of study with typical jitter of 68fs for a 1.8V 80dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.
Versión del editorhttp://dx.doi.org/ 10.1007/s10470-016-0870-6
URIhttp://hdl.handle.net/10261/138318
DOI10.1007/s10470-016-0870-6
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